In order for computers to function, the integrated circuit industry must manufacture memory integrated circuits (ICs) or integrated circuits which contain memory cells so that data can be stored. This stored data is then manipulated by a central processing unit (CPU) IC to perform useful operations. One type of memory cell manufactured by the integrated circuit industry for the computer industry is referred to as a ferroelectric memory cell.
Ferroelectric memory cells are characterized via a hysteresis loop as illustrated in FIG. 1. FIG. 1 illustrates a dashed line which is a hysteresis loop extending from -5 volts to 5 volts. When the two capacitor electrodes of the ferroelectric capacitor are biased to a differential voltage of +5 volts, a positive charge is stored into the capacitor. If this voltage is then removed from 5 volts to 0 volts, the capacitor retains a positive charge or polarity as indicated in a top portion of FIG. 1 when the voltage is zero. If the voltage across the ferroelectric capacitor is pushed to -5 volts and then released to 0 volts, the charge stored in the ferroelectric device will be negative as indicated via a bottom portion of the polarization axis in FIG. 1 when voltage is zero. Therefore, the ferroelectric dielectric between the two conductive capacitor electrodes may be programmed into one of two states (a logic zero and a logic one) depending upon a previously applied voltage (either +5 v or -5 v).
These ferroelectric memory cells are advantageous since they have a small cell surface area in a manner similar to a DRAM, require no refreshing circuitry as does a DRAM, are non-volatile and will not lose charge or data when power is turned off as does a DRAM, are more radiation hard and have reduced soft error rate when compared to DRAMs, and have other advantages over DRAM cells and other like memory cell structures. However, ferroelectric cells have not been widely integrated into existing integrated circuit designs or into existing computer designs partly for the reason that simulation and design of these ferroelectric circuits are either inadequate or difficult to implement. A circuit designer cannot design a ferroelectric capacitor into a process flow and integrated circuit layout if the ferroelectric cell cannot be properly modeled while in the design phase.
FIG. 1 illustrates a prior art method of modeling a hysteresis loop referred to as the Miller model. The Miller model fits the major hysteresis loop indicated in FIG. 1 by the dashed line, and all minor internal hysteresis loops in FIG. 1 using an equation P=P.sub.0 .times.tanh (F(V))+C.sub.0 .times.V, where P=polarization, P.sub.0 =maximal polarization, F(V) is some function of voltage, C.sub.0 =capacitance, and V=the operating voltage of the model. FIG. 1 illustrates that when using this hyperbolic tangent model, loop walking 10 can occur where the loop walking is highly inaccurate to actual physical operation. To illustrate the loop walking phenomenon, assume that the capacitor which results in the hysteresis curve of FIG. 1 is charged to 5 volts. After being exposed to 5 volts, the voltage is dropped to 0 and then the voltage is subsequently oscillated between -0.3 volts and +0.3 volts as illustrated in FIG. 1. Using the Miller model, instead of the model retaining charge for the small sinusoidal -0.3 volts to +0.3 volts oscillation, the Miller model will decay the charge or walk the minor hysteresis loops towards zero polarization as indicated in FIG. 1. This is physically incorrect since the ferroelectric cell should maintain a small hysteresis loop in the vicinity of the current polarization without polarization falling to zero over time. In addition, the curve 10 is not even in the shape of a minor hysteresis loop which is also a fatal flaw of the model.
Therefore, any complicated voltage function applied to a ferroelectric capacitor over time cannot be modeled by the Miller model. This loop walking and minor loop shape distortion which results from the Miller model results in the Miller model not being effective for ferroelectric circuit design. In essence, any design cycle using the Miller model is time inefficient and ineffective and may result in a manufactured part that does not yield properly unless the design process is iterated many times.
FIG. 2 illustrates another hysteresis curve which is similar to the hysteresis curve illustrated in FIG. 1. FIG. 2 is used to illustrate that linear interpolations or linear approximations are used by circuit designers to model hysteresis curves for ferroelectric capacitors. Instead of closely following the curvature and shape and the hysteresis curve, the linear model assumes that there is a straight line between a maximum voltage/charge point on the upper right hand corner of the hysteresis curve and at zero voltage programmed point which results in either a binary zero value or a binary one value depending upon the resulting polarization. Although this model allows for very rough estimation of the functionality of a ferroelectric capacitor, it is inadequate to form complicated ferroelectric circuits and precise ferroelectric models so that ferroelectric circuits can be manufactured with high yield and in a time efficient manner. In general, the linear approach to modeling any non-linear electrical device, while simple and easy to calculate, is usually always inadequate and results in erroneous manufacture and faulty operation of integrated circuit devices. Therefore, a non-linear device designed and manufactured using a linear model will most likely not work when first manufactured and will have to be iteratively manufactured many times resulting in wasted time and wasted money in order to optimize the design for real world conditions.
Another method used in the prior art is a Gaussian surface integral model developed by Zurcher et al. This model is illustrated in FIG. 3 herein. FIG. 3 illustrates that a ferroelectric capacitor, when designed into an integrated circuit, comprises a ferroelectric capacitor portion and a load/bit line capacitor portion. These capacitor portions may be spliced into a plurality of infinitesimal or thin Gaussian surfaces which can each be characterized by a plurality of parameters such as dielectric constants, E-field, thickness of layer, coercive field, and spontaneous polarization, etc. This model is computationally intensive and parameterization of the model is incredibly difficult. This model requires solving large matrices many times (1000-3000 times) and requires several (50-100) parameters stored in memory at any given time. When simulating the circuit, the voltage across the ferroelectric model will change often and every incremental voltage across the capacitor will require the Zurcher model to calculate hundreds if not thousands of computations in order to correct the model to provide for a correct charge in the capacitor in response to the changing voltage. Because of the computationally intensive operation, it is impossible for the Zurcher model to be used in a time efficient manner within an actual circuit simulator since simulation times would be significantly increased by using the Zurcher model to the point where the circuit designer could not feasibly iterate multiple designs and solve problems using this time consuming simulation model. One can easily appreciate the time consuming calculation intensive nature of the Zurcher model by observing the resulting Zurcher equations below for only seven Gaussian surfaces: ##EQU1##
It is apparent that the Miller model, linear model, and Zurcher model, which are either used for the design of ferroelectric circuits or are being considered for use in designing ferroelectric circuits, are inadequate for designing ferroelectric devices in a time efficient and cost effective manner. The need exists in the art for an improved ferroelectric model which does not loop walk or have shape incorrectness as does the Miller model, which is more accurate than the linear approximations used in the past, and is less computationally intensive than the Zurcher model, while being computationally manageable, accurate, and time/cost effective.